Semiconductor industry HKMG battle: the two craft schools struggle 2
The different views of experts, including the company's Technical Director JohnPellerin GlobalFoundries, who emphasized the Gate-first process does not require circuit design circuit design on the side to change too much, and the performance is also fully able to meet the requirements of 32/28nm node process .
Pellerin stressed: "We definitely will use the 28nm process node, Gate-first process. The reason is that our customers want to switch to HKMG structure to avoid excessive design changes."
The TSMC's technology executives Jiangshang Yi said that a similar problem the industry has experienced 20 years ago: "The industry has also found that N + doped Vt PMOS gate material causes a higher voltage, so that some companies in the industry began to channel the doping impurities to suppress the Vt, the result has brought a lot of side effects such as causing short-channel effect is more obvious and so on. "The current Gate-first technology program produced HKMG transistors the situation is with this very Similarly, although it can be used to join the overlying layers, etc. to improve the Gate-first high Vt process likely to cause problems, but adding the coating process is very complex and difficult to master. Therefore, the TSMC simply choose to turn Gate-last process, but Gate-last process is implemented if you want to maintain Gate-first technology products, die density approximation, requires the circuit designer Layout redesign.
Expert opinion:
Gartner's semiconductor industry analyst DeanFreeman said: "TSMC turned Gate-last, example of this process in terms of performance, or there is a certain superiority. Although Gate-first technology products made of die density more advantages, but must continue to apply this technology there are some insurmountable problems of TSMC. "
Organization of the European School of Microelectronics Centre IMEC high-k technology for research and development director ThomasHoffmann had IEDM2009 conference pointed out the Gate-first technology shortcomings in terms of performance, but in an interview after the meeting, he said that despite the Gate-first some performance shortcomings, but the performance is not very sensitive part of the first power device is able to meet the requirements.
He said: "The development of Renesas low-power devices such as companies, perhaps Gate-first process is the better choice. Such devices generally Vt value and performance of the tube is not too high demands. But when product development process to the 28nm node level and above, these companies will need to move to Gate-last. "but" on the pursuit of performance-based vendors, Gate-last is the inevitable choice. IBM's product clearly is that type, so I think if they do not use the Gate-last, then it must be the issue of how to reduce Vt come up with better ways. Of course, the complexity of this program will be greater, but also may affect the product yield . and finally they may be backward Gate-last process, which is IBMFishkill production technology alliance partners are worried about. "
According to Hoffmann introduced, although in Gate-last process, manufacturers of etching and chemical polishing in the (CMP) process step will encounter some problems, but the Gate-first technology is not out of trouble. As mentioned earlier, the current Gate-first process although good control of Vt, they are not completely impossible, the main means by setting a certain thickness of high-k insulator coating (caplayer) to realize that this program needs In the high-k layer deposited oxide thin upper and lower positions. For example, in NMOS tube would require high-k layer in the upper sediment layer of thickness less than 1nm of La2O3 thin layer, to achieve the purpose of adjusting the voltage Vt; in PMOS tube, you need to work through the steps to the etching thin layer removed and replaced with Al2O3 thin layer of material, this will require sophisticated technology to control how the PMOS thin tube will be removed without affecting the NMOS of the overlying layer.
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