Magnetic core memory – Disposable Tooth Scaler – Nose Rinsing Device
History
Frederick Viehe claimed the first patent of the magnetic core memory in 1947, having developed the device in his home laboratory. Separately, substantial work in the field was carried out by the Shanghai-born American physicists, An Wang and Way-Dong Woo, who created the pulse transfer controlling device in 1949. The name referred to the way that the magnetic field of the cores could be used to control the switching of current in electro-mechanical systems. Wang and Woo were working at Harvard University’s Computation Laboratory at the time, but unlike MIT, Harvard was not interested in promoting inventions created in their labs. Instead Wang was able to patent the system on his own while Woo took ill.
Jay Forrester’s group, working on the Whirlwind project at MIT, became aware of this work. This machine required a fast memory system for realtime flight simulator use. At first, Williams tubes (more accurately, Williams-Kilburn tubes) a storage system based on cathode ray tubes were used, but these devices were always temperamental and unreliable.
Two key inventions led to the development of magnetic core memory in 1951, which enabled the development of computers as we know them. The first, An Wang’s, was the write-after-read cycle, which solved the puzzle of how to use a storage medium in which the act of reading was also an act of erasure. The second, Jay Forrester’s, was the coincident-current system, which enabled a small number of wires to control a large number of cores (see Description section below for details).
Forrester’s coincident-current system required one of the wires to be run at 45 degrees to the cores, which proved impossible to wire by machine, so that core arrays had to be assembled by workers with fine motor control under microscopes. Initially, garment workers were used.
It was during the early 50s that Seeburg developed the use of this coincident current ferrite core memory storage in the ‘Tormat’ memory of its new range of jukeboxes, starting with the V200 released in 1955. Development work was completed in 1953.
By the late 1950s industrial plants had been set up in the Far East to build core. Inside, hundreds of workers strung cores for low pay. This lowered the cost of core to the point where it became largely universal as main memory by the early 1960s, replacing both the low-cost and low-performance drum memory as well as the high-cost and high-performance systems using vacuum tubes, later transistors, as memory. Certain manufacturers also employed Scandinavian seamstresses who had been laid off due to mechanization of the textile industry.
The cost of core memory declined sharply over the lifetime of the technology: costs began at roughly US$1.00 per bit and eventually approached roughly US$0.01 per bit. Core was in turn replaced by integrated silicon RAM chips in the 1970s.
Dr. Wang’s patent was not granted until 1955, and by that time core was already in use. This started a long series of lawsuits, which eventually ended when IBM paid Wang several million dollars to buy the patent outright. Wang used the funds to greatly increase the size of Wang Laboratories which he co-founded with Dr. Ge-Yao Chu, a school mate from China.
Core memory was part of a family of related technologies, now largely forgotten, which exploited the magnetic properties of materials to perform switching and amplification. By the 1950s vacuum-tube electronics was well-developed and very sophisticated, but tubes had a limited lifetime, used a lot of power, and their operating characteristics changed in value over their life. Magnetic devices had many of the virtues of the transistor and solid-state devices that would replace them, and saw considerable use in military applications. A notable example was the portable (truck-based) MOBIDIC computer developed by Sylvania for the United States Army Signal Corps in the late 1950s. Core memory was non-volatile: the contents of memory were not lost if the power supply was interrupted or the software crashed.
Description
How core memory works
The most common form of core memory, X/Y line coincident-current used for the main memory of a computer, consists of a large number of small ferrite (ferromagnetic ceramic) rings, cores, held together in a grid structure (each grid called a plane), with wires woven through the holes in the cores’ middle. In early systems there were four wires, X, Y, Sense and Inhibit, but later cores combined the latter two wires into one Sense/Inhibit line. Each ring stores one bit (a 0 or 1). One bit in each plane could be accessed in one cycle, so each machine word in an array of words was spread over a stack of planes. Each plane would manipulate one bit of a word in parallel, allowing the full word to be read or written in one cycle.
Core relies on the hysteresis of the magnetic material used to make the rings. Wires that pass through the cores create magnetic fields. Only a magnetic field greater than a certain intensity (“select”) can cause the core to change its magnetic polarity. To select a memory location, one of the X and one of the Y lines are driven with half the current (“half-select”) required to cause this change. Only the combined magnetic field generated where the X and Y lines cross is sufficient to change the state; other cores will see only half the needed field, or none at all. By driving the current through the wires in a particular direction, the resulting induced field forces the selected core’s magnetic flux to circulate in one direction or the other (clockwise or counterclockwise). One direction is a stored 1, while the other is a stored 0.
Close-up of a core plane similar to the one shown at top. The distance between the rings is roughly 1 mm (0.04 in). The green horizontal wires are X; the Y wires are dull brown and vertical, toward the back. The sense wires are diagonal, colored orange, and the inhibit wires are vertical twisted pairs.
Reading and writing
Reading from core memory is somewhat complex. Basically the read operation consists of doing a “flip to 0” operation to the bit in question, that is, driving the selected X and Y lines in the direction that causes the core to flip to whatever polarity the machine considers to be zero. If the core was already in the 0 state, nothing will happen. However if the core was in the 1 state it will flip to 0. If this flip occurs, a brief current pulse is induced into the Sense line, saying, in effect, that the memory location used to hold a 1. If the pulse is not seen, that means no flip occurred, so the core must have already been in the 0 state. Note that every read forces the core in question into the 0 state, so reading is destructive, which is one of the attributes of core memory.
Writing is similar in concept, but always consists of a “flip to 1” operation, relying on the memory already having been set to the 0 state in a previous read. For the write operation, the current in the X and Y lines goes in the opposite direction as it did for the read operation. If the core in question is to hold a 1, then the operation proceeds normally and the core flips to 1. However if the core is to instead hold a zero, the same amount of current as is used on the X and Y lines is also sent into the Inhibit line, which drops the combined field from the X, Y and Inhibit lines to half of the field needed to flip the core magnetization state. This leaves the core in the 0 state.
Note that the Sense and Inhibit wires are used one after the other, never at the same time. For this reason later core systems combined the two into a single wire, and used circuitry in the memory controller to switch the duty of the wire from Sense to Inhibit.
A fundamental principle of core memory is that each read must be followed immediately by a write, to restore the value that is always destroyed by the read operation. Many computers began to include instructions that took advantage of this fact; if a location was going to be read, changed and re-written (for example by an increment operation), the computer would ask the memory controller to do the read, but then signal it to pause before doing the write that would normally follow. Once the increment instruction was complete the controller would be unpaused, and the usual write would occur, but using the new value. For certain types of operations, this effectively doubled the performance.
Other forms of core memory
Word line core memory was often used to provide register memory. This form of core memory typically wove three wires through each core on the plane, word read, word write, and bit sense/write. To read or clear words, the full current is applied to one or more word read lines; this clears the selected cores and any that flip induce voltage pulses in their bit sense/write lines. For read, normally only one word read line would be selected; but for clear, multiple word read lines could be selected while the bit sense/write lines ignored. To write words, the half current is applied to one or more word write lines, and half current is applied to each bit sense/write line for a bit to be set. For write, multiple word write lines could be selected. This offered a performance advantage over X/Y line coincident-current in that multiple words could be cleared or written with the same value in a single cycle. A typical machine’s register set usually used only one small plane of this form of core memory.
Another form of core memory called core rope memory provided read-only storage. In this case, the cores were simply used as transformers; no information was actually stored magnetically within the individual cores. An example was the Apollo Guidance Computer used for the moon landings.
Physical characteristics
The performance of early core memories can be characterized in today’s terms as being very roughly comparable to a clock rate of 1 MHz (equivalent to early 1980s home computers, like the Apple II and Commodore 64). Early core memory systems had cycle times of about 6 s, which had fallen to 1.2 s by the early 1970s, and by the mid-70s it was down to 600 ns (0.6 s). Everything possible was done in order to increase access, including the simultaneous use of multiple grids of core, each storing one bit of a data word. For instance a machine might use 32 grids of core with a single bit of the 32-bit word in each one, and the controller could access the entire 32-bit word in a single read/write cycle.
Core memory is non-volatile storage it can retain its contents indefinitely without power. It is also relatively unaffected by EMP and radiation. These were important advantages for some applications like first generation industrial programmable controllers, military installations and vehicles like fighter aircraft, as well as spacecraft, and led to core being used for a number of years after availability of semiconductor MOS memory (see also MOSFET). For example, the Space Shuttle flight computers initially used core memory, which preserved the contents of memory even through the Challenger’s explosion and subsequent plunge into the sea in 1986.
A characteristic of core was that it is current-based, not voltage-based. The “half select current” was typically about 400 mA for later, smaller, faster cores. Earlier, larger cores required more current.
Another characteristic of core is that the hysteresis loop was temperature sensitive: the proper half select current at one temperature is not the proper half select current at another temperature. So the memory controllers would include temperature sensors (typically a thermistor) to adjust the current levels correctly for temperature changes. An example of this is the core memory used by Digital Equipment Corporation for their PDP-1 computer; this strategy continued through all of the follow-on core memory systems built by DEC for their PDP line of air-cooled computers. Another method of handling the temperature sensitivity was to enclose the magnetic core “stack” in a temperature controlled oven. Examples of this are the heated air core memory of the IBM 1620 (which could take up to 30 minutes to reach operating temperature, about 106 F, 41 C) and the heated oil bath core memory of the IBM 7090, early IBM 7094s, and IBM 7030.
It is sometimes wondered why the core was heated instead of cooled. This was because the primary requirement was a consistent temperature, and it was easier (and cheaper) to maintain a constant temperature well above room temperature than one at or below it.
In 1980, the price of a 16 kW (kiloword, equivalent to 32kB) core memory board that fitted into a DEC Q-bus computer was around USD 3000. At that time, core array and supporting electronics fit on a single printed circuit board about 25 x 20 cm in size, the core array was mounted a few mm above the PCB and was protected with a metal or plastic plate.
Diagnosing hardware problems in core memory required time-consuming diagnostic programs to be run. While a quick test checked if every bit could contain a one and a zero, these diagnostics tested the core memory with worst-case patterns and had to run for several hours. As most computers had just a single core memory board, these diagnostics also moved themselves around in memory, making it possible to test every bit. In many occasions, errors could be resolved by gently tapping the printed circuit board with the core array on a table. This slightly changed the position of the cores to the wires running through and could fix the problem. The procedure was seldom needed, as core memory proved to be very reliable compared to other computer components of the day.
See also
Wikimedia Commons has media related to: Core memory
Delay line memory
Core dump
Core rope memory
Twistor memory
Bubble memory
Thin film memory
MRAM
Ferroelectric RAM
Electronic Calculators Some early desktop models used magnetic core memory.
References
^ Edwin D. Reilly, “Milestones in computer science and information technology”, Greenwood Press: Westport, CT, 2003, p. 164, ISBN 1573565210
Patents
U.S. Patent 2,667,542 “Electric connecting device” (matrix switch with iron cores), filed September 1951, issued January 1954
U.S. Patent 2,708,722 “Pulse transfer controlling devices”, An Wang filed October 1949, issued May 1955
U.S. Patent 2,736,880 “Multicoordinate digital information storage device” (coincident-current system), Jay Forrester filed May 1951, issued February 28, 1956
U.S. Patent 3,161,861 “Magnetic core memory” (improvements) Ken Olsen filed November 1959, issued December 1964
U.S. Patent 4,161,037 “Ferrite core memory” (automated production), July 1979
U.S. Patent 4,464,752 “Multiple event hardened core memory” (radiation protection), August, 1984
External links
Interactive Java Tutorial – Magnetic Core Memory National High Magnetic Field Laboratory
Core Memory at Columbia University
Navy Manual
Core Memory on the PDP-11
Core memory and other early memory types accessed April 15, 2006
Coincident Current Ferrite Core Memories Byte magazine, July 1976
Casio AL-1000 calculator Shows close-ups of the magnetic core memory in this desktop electronic calculator from the mid-1960s.
Still used core memory in multiple devices in a German computer museum
A 110-Nanosecond Ferrite Core Memory
v d e
Magnetic storage media
Wire (1898) Tape (1928) Drum (1932) Ferrite core (1949) Hard disk (1956) Stripe card (1956) MICR (1956) Thin film (1962) CRAM (1962) Twistor (~1968) Floppy disk (1969) Bubble (~1970) MRAM (1995) Racetrack (2008)
Categories: Computer memory | Non-volatile memory
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