Radar Video accumulation algorithm implementation on FPGA – Radar, Video, FPGA-H
1 Introduction As radar complexity of their environment, in addition to surface object, clouds and rain, birds and other disturbances, but also may come from nearby radar asynchronous interference, radio interference. All the interference, through the receiver into the signal processor, despite the intermediate frequency signal processing, but there may be residual. Therefore, in order to obtain better detection performance, detection of the accumulation before a video is necessary. Although the effect of accumulated
video as coherent integration, but the video is relatively simple to achieve accumulation of the project, on the radar transceiver system is not strictly coherent requirements, and the majority of moving target in terms of its ups and downs will clearly echo destruction of adjacent phase-coherent echo signals, therefore, in many practical engineering applications, or use video accumulation.
Accumulation algorithm of radar video project implementation process, the need for radar signal processor with a faster real-time, and stability of the signal processor, size, power consumption, there are strict requirements. Recent years, with the rapid development of FPGA technology to provide us with a better way to solve this problem. As the FPGA itself with the parallel structure of the arithmetic structure, particularly suitable for making high-performance FPGA data path processor. Using FPGA to achieve real-time radar video integration algorithm is strong, the hardware system is small and flexible structure suitable for modular design, development and short, and supports online programmable, so that the system has strong universal scalability advantages. This article as a starting point, and discuss a proposed use of FPGA technology radar video accumulation method.
2 hardware structure Realization process in the main core using a FPGA-based signal processing card up, both collected from the radar receiver IF and video signal and its digital signal processing, and can produce their own simulation of radar frequency, video signal processing digital signal processing or direct to the radar signal processor. Radar signal processing hardware block diagram of the card shown in Figure 1.
FPGA is used in the company's 1 million Xilinx FPGA chip, XC3S1000, its configuration for the Xilinx chip companies 1Mb capacity PROM chip XC18V01, serial way to take the initiative power FPGA for configuration. AD, DA, respectively ADI company's 12-bit high speed ADC chip AD9432 and 14-bit high-speed digital-analog converter chip AD9764SRAM using Cypress's 256k × 16bSRAM chip CYTC1041.
FPGA design to achieve 32b/33MHz using the PCI interface logic, real-time signal acquisition and transmission control. As the FPGA with hierarchical memory systems, the basic logic function blocks can be configured into a 16 × 1,16 × 2 or 32 × 1 synchronous RAM, or 16 × 1 dual-port synchronous RAM, it can double in the high-speed FPGA internal configuration port RAM is used as the signal transmission of the data buffer. Meanwhile, in order to save FPGA's internal logic resources, the external configuration of the FPGA SRAM to store the appropriate data.
3 video integration algorithm in FPGA implementation on
Usually works accumulated video There are many ways to achieve. From the time domain, the video is a continuous accumulation of N repeats the same cycle of the video echo signal from the unit were superimposed, so accumulation can not do without delay line to achieve pulse train. Using FPGA digital delay line, the need to cycle the previous N-1 signals quantified stored, which requires large storage and computation. Therefore, in practical engineering, often based on sliding window detector for antenna beam sweeps target echo pulses received less N occasion, but if the value is still larger N, the sliding window detector needs to have a great storage. Therefore, use of FPGA to realize video was accumulated by a small sliding window detector is more suitable for FPGA features.
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