Altera release 28-nm Stratix V FPGA family – Hydraulic Couplings Manufacturer – Turned parts Manufacturer
Altera Corporation (NASDAQ: ALTR) today announced the industry's largest bandwidth, FPGA – the next generation 28-nm Stratix? V FPGA. Stratix V FPGA serial switching capacity with 1.6 Tbps, using a variety of innovative technologies and cutting-edge 28-nm process, decreasing cost and power broadband applications.
Stratix V FPGA family using TSMC 28-nm high-performance (HP) technology to make, to provide 1.1 million logic elements (LE) ,53-Mbits of embedded memory, 3,680 a 18×18 multipliers, and working in the industry's highest integration rate of 28 Gbps transceiver. Device also features the industry's most advanced dedicated hard core intellectual property (IP), enhanced system integration and performance, without cost and power consumption costs. The series includes four models to meet the wireless / wireline communications, broadcast, computer and storage, test and market a variety of medical applications. These models include:
? Stratix V GT FPGA – the industry's only system for more than 100G, integrated 28-Gbps transceiver FPGA.
? Stratix V GX FPGA – to support multiple applications, 600-Mbps to 12.5-Gbps transceiver.
? Stratix V GS FPGA – 600-Mbps to 12.5-Gbps transceiver for high-performance digital signal processing (DSP) applications.
? Stratix VE FPGA – suitable for ASIC prototyping and simulation, as well as high-performance computing applications in high-density FPGA.
Altera's products and vice president of enterprise market Vince Hu commented: "We are fifth generation Stratix series of innovative technologies greatly improve the density of high-end devices and I / O performance, and further consolidate the FPGA compared to ASIC and ASSP's competitive position. Altera has been working to raise the bandwidth cost and power consumption while meeting the design requirements of this problem. from the core to the I / O, we study the Stratix V FPGA all the indicators, to ensure that the device has the best performance, density and integration. "
Stratix V FPGA: the bandwidth of the building
Stratix V GX and Stratix V GS FPGA contains 66 high-performance, low power 12.5 Gbps transceiver. Stratix V FPGA to support a variety of 3G, 6G and 10G protocol and electrical standards, to meet the compatibility requirements, for example, 10G/40G/100G, Interlaken, and PCI Express (PCIe) Gen 3, Gen2, Gen 1. The device also supports and 10G backplane (10GBASE-KR) and optical modules direct link. Stratix V GT FPGA's 28-Gbps transceiver designed to meet the CEI-28G specification. 28-Gbps transceiver power consumption per channel is only 200 mW, significantly reduce the bandwidth of the system unit power.
In addition to transceiver bandwidths, Stratix V FPGA also includes a 7 x 72 1,600-Mbps DDR3 memory interface, and all I / O at 1.6 Gbps LVDS channels.
Altera Stratix V FPGA on the core architecture improvements, increased efficiency of space and logic, and system performance, including:
? New adaptive logic module (ALM) architecture – the largest device in a 800K register additional enhanced logic efficiency. ALM architecture requires a large number of lines and applied to register the design.
? With M20K embedded memory modules increase the structure – an area of increased efficiency, better performance.
? The industry's first DSP module with adjustable accuracy – achieve the highest efficiency, the best performance of multi-precision DSP data path.
? User-friendly part of the re-configuration – designers can reconfigure part of the FPGA, while the other part is still running.
If you need to know about Stratix V FPGA architecture more information, please visit: <http://www.altera.com.cn/stratix5>.
Stratix V FPGA to implement all the FPGA of the most integrated hard core IP, improved device performance, there is no power or cost of the price. Device enhancements including PCIe Gen3, Gen2, Gen1, 40G/100G Ethernet, CPRI / OBSAI, Interlaken, Serial RapidIO (SRIO) 2.0 and Gigabit Ethernet (GbE) 10GBASE-R. Enhanced read / write access to memory interface including DDR3, RLDRAM II and QDR II +.
As announced earlier this year, Altera 28-nm FPGA innovative technology, Stratix V FPGA embedded with the company's HardCopy module. This unique method to quickly change the Altera FPGA in the enhancement in 3 to 6 months to complete specific device model development. Embedded HardCopy module provides the user with 700K equivalent to LE, as compared with the soft core logic to achieve lower power consumption by 65%.
Transition to a HardCopy ASIC
Altera Stratix V FPGA also provide HardCopy V ASIC devices to help them to lower risk and cost of transition to ASIC products. Company as soon as possible HardCopy V ASIC details.
Availability
Altera is expected in the first quarter of 2011 on sale Stratix V FPGA samples. The second quarter of 2010, the Quartus? II 10.0 software, provide support for Stratix V FPGA. About Altera high-performance FPGA family details
Please contact your local Altera sales representative, or visit http://www.altera.com.cn/stratix5.
Series of white papers, video and technical documentation highlighted Stratix V FPGA how to help you solve the most difficult design challenges, Altera web site you can access this information. If you need information and Stratix V FPGA variety of other letters
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